The present invention relates to an output circuit, and more particularly, to an improvement of an output voltage level of a circuit for amplifying and outputting a logical signal and the like.
A multi-function and high-performance data processing unit has been demanded recently as the quantity of information increases, and the processing unit, generally having a semiconductor integrated circuit device Including N- and P-channel type field effect transistors formed with high accumulation and high density, is packaged on a printed circuit board and the like, and output terminals of these field effect transistors are connected to a common bus for use.
In such a case, power supply control is sometimes adopted such that the output operation of the relevant semiconductor integrated circuit device is sustained and the output operation of another semiconductor integrated circuit device is continued. As a result, the output level of a common bus is lowered sometimes, caused by a forward diode of a transistor connected to a power supply line of the semiconductor integrated circuit device in which the output operation has been sustained.
Further, a tendency that output circuits, which are to satisfy the standard of RS422 are integrated, is shown. With a tendency, an output circuit using N-channel type field effect transistors is the likeliest, but the output level at the time of normal operation is lowered sometimes, due to dependency of the backgate thereof.
Thus, an output circuit which is able to cut off a current passage with a forward parasitic diode of a transistor connected to one of a power supply line and a ground line as a path and is also able to lower the output low level to the utmost by increasing the output high level to the utmost at the time of normal output operation is desired.
FIGS. 39(a) to 41(b) are explanatory diagrams related to conventional examples. FIGS. 39(a) and 39(b) are explanatory diagrams of a first output circuit related to a conventional example and a semiconductor integrated circuit thereof.
FIG. 39(a) shows a complementary output circuit (CMOS circuit) such as a buffer circuit and a bus driver circuit for amplifying and outputting an input signal. The relevant output circuit is composed of, for example, P-channel and N-channel MOS transistors (hereinafter referred to simply as a first and second transistors) Tp and Tn connected in series between a power supply line Vcc and a ground line GND as shown in FIG. 39(a). Besides, a backgate BG of the first transistor Tp is connected to the power supply line Vcc, and a backgate BG of the second transistor Tn is connected to the ground line GND. This is made for the purpose of preventing an electrical floating state of the first and the second transistors Tp and Tn from being produced.
The function of the relevant circuit is such that, when a high ("H") level is inputted to the gates G1, G2 of the first and the second transistors Tp and Tn as an input signal, an output signal=low ("L") level is outputted at drain D=output terminal out of both transistors Tp and Tn. Further, when an "L" level is inputted to the gates G1, G2 of the first and the second transistors Tp and Tn as an input signal, an output signal="H" level is outputted at the drain D=output terminal out of both transistors Tp and Tn. With this, a logical signal and the like applied to an input terminal in are amplified and outputted.
Besides, D1 represents a first parasitic diode, which is a forward junction being parasitic between the drain D and the power supply line Vcc when the first transistor Tp is seen from the output terminal out. Further, D2 represents a second parasitic diode, which is a forward junction being parasitic between the drain D and the ground line GND when the second transistor Tn is seen from the output terminal out.
FIG. 39(b) shows a sectional structural view of a semiconductor device of the relevant output circuit. In FIG. 39(b), a semiconductor device in which the output circuit is integrated is provided with, for example, the first transistor Tp and the second transistor Tn on an n-type semiconductor substrate 1.
The first transistor Tp includes a pair of P.sup.+ type diffused layers 3A and 3B and an N.sup.+ type diffused layer (backgate lead electrode) 4A in the n-type semiconductor substrate 1, and a first gate electrode 6A is provided on the channel regions of the P.sup.+ type diffused layers 3A and 3B through a first gate oxide film 5A.
The second transistor Tn includes a pair of N.sup.+ type diffused layers 3C and 3D and a P.sup.+ type diffused layer (backgate lead electrode) 4B in a P.sup.+ -well layer 2, and a second gate electrode 6B is provided on the channel regions of the N.sup.+ type diffused layers 3C and 3D through a second gate oxide film 5B.
Further, one P.sup.+ type diffused layer 3A of the first transistor Tp and one N.sup.+ type diffused layer 3C of the second transistor Tn are connected to each other and extended to the output terminal out. The other P.sup.+ type diffused layer 3B and the N.sup.+ type diffused layer 4A of the first transistor Tp are connected to each other and further to the power supply line Vcc, and the other N.sup.+ type diffused layer 3D and the P.sup.+ diffused layer 4B of the second transistor Tn are connected to each other and extended to the ground line GND.
Besides, the first parasitic diode D1 is a pn junction being parasitic among the P.sup.+ diffused layer 3B of the first transistor Tp, the N-type semiconductor substrate 1 and the N.sup.+ type diffused layer 4A. Further, the second parasitic diode D2 is a pn junction being parasitic among the N.sup.+ type diffused layer 3D, the P-well layer 2 and the P.sup.+ diffused layer 4B.
FIGS. 40(a) and 40(b) are explanatory diagrams of a second output circuit related to a conventional example and a semiconductor integrated circuit device thereof.
FIG. 40(a) shows an output circuit such as a buffer circuit and a bus driver circuit for amplifying and outputting an input signal. The relevant output circuit is composed of, for example, N-channel MOS transistors (hereinafter referred to simply as the first and the second transistors) TN1 and TN2 connected in series between the power supply line Vcc and the ground line GND as shown in FIG. 40(a). Besides, backgate BG of the first and the second transistors TN1 and TN2 are connected to each other, which are connected further to the ground line GND.
The function of the relevant circuit is such that, when a high ("H") level is applied as an input signal to the gate G of the first transistor TN1 and a low ("L") level is applied to the gate G of the second transistor TN2, an output signal="H" level is outputted at the drain D=output terminal out of both transistors TN1 and TN2. Further, when an "L" level is inputted to the gate G of the first transistor TN1 and a "H" level is inputted to the gate G of the second transistor TN2, an output signal="L" level is outputted at the output terminal out of both transistors TN1 and TN2. With this, a logical signal and the like applied to the input terminal in are amplified and outputted. Besides, Dn represents a parasitic diode, which is a forward junction being parasitic between the drain D and the ground line GND when the second transistor TN2 is seen from the output terminal out.
FIG. 40(b) shows a sectional structural view of a semiconductor device of the relevant output circuit. In FIG. 40(b), the semiconductor device with the output circuit accumulated therein is provided with, for example, the first transistor TN1 and the second transistor TN2 in an n-type semiconductor substrate 1.
The first transistor TN1 includes a pair of first n-type diffused layers 3E and 3F and a first P.sup.+ type diffused layer (backgate lead layer) 4C in a first P-well layer 2A, and a first gate electrode 6C is provided on channel regions of the N.sup.+ type diffused layers 3E and 3F through a first gate oxide film 5C.
The second transistor TN2 includes a pair of second N.sup.+ type diffused layers 3G and 3H and a second P.sup.+ type diffused layer (backgate lead electrode) 4D in a second P-well layer 2B, and a second gate electrode 6D is provided on channel regions of the N.sup.+ type diffused layers 3G and 3H through a second gate oxide film 5D.
Further, one N.sup.+ type diffused layer 3E of the first transistor TN1 and one N.sup.+ type diffused layer 3G of the second transistor T2 are connected to each other and extended to the output terminal out, the other N.sup.+ type diffused layer 3F of the transistor TN1 is connected to the power supply line Vcc, and the other N.sup.+ type diffused layer 3H and the second P.sup.+ type diffused layer 4D of the second transistor TN2 are connected to each other and extended further to the ground line GND.
Besides, the parasitic diode Dn represents a pn junction being parasitic among the N.sup.+ type diffused layer 3H, the first P-well layer 2B and the first P.sup.+ type diffused layer 4D, and the output impedance is increased because the parasitic diode Dn is reversed in direction when the first and the second transistors TN1 and TN2 are seen from the output terminal out.
Now, in a conventional example, a semiconductor integrated circuit device, on which the first output circuit is integrated, is packaged on a printed circuit board and the like, and the output terminals out thereof are connected to a common bus 9 for use, sometimes, as shown In FIG. 41(a). At this time, power supply control, such that the output operation of a semiconductor integrated circuit device 7 is sustained and the output operation of another semiconductor integrated circuit device 8 is continued, is adopted sometimes.
In this case, the first power supply line Vcc1 of the semiconductor integrated circuit device 7 is deactivated (OFF) so as to stop the output operation thereof and the second power supply line Vcc2 of another semiconductor integrated device 8 is activated (ON) so as to continue the output operation thereof due to the necessity of selecting the logical output signal.
As a result, it sometimes happens that the output "H" level of the common bus 9 is lowered because of the first parasitic diode (forward diode) D1 of the semiconductor integrated circuit device 7 in which the output operation is sustained. It is conceivable to occur because of the reason that a forward current i, that charges wiring capacitor CO and the like of the power supply line Vcc1 by flowing from the output terminal out of the semiconductor integrated circuit device 7 through the first parasitic diode D1 of the device 7 at time when the output operation has been stopped (FIG. 41(a)).
This poses a first problem that the output "H" level outputted from another semiconductor integrated circuit device 8 to the common bus 9 is lowered remarkably unless the output impedance of the semiconductor integrated circuit device 7 in which the output operation has been sustained is increased.
Further, the output circuit composed of the first and the second transistors TN1 and TN2 having a high output impedance when seen from the output terminal out, i.e., the output circuit which is to satisfy the standard of RS422 (high speed operation standard) is integrated, as shown in FIG. 40(a), solves the first problem.
However, there is a second problem in that the output "H" level at the time of normal operation is lowered due to dependency of the backgate BG of the first and the second transistors TN1 and TN2. In this case, when in "H" level is applied to the gate G of the first transistor TN1, the voltage level at the output terminal out should be ideally at 4.2(V), obtained by subtracting a threshold voltage Vth=voltage drop at one stage in case it is assumed that the threshold voltage Vth of the first transistor TN1 is Vth=0.8(V) and the potential of the power supply line is at 5(V) for instance, but the voltage level is lowered to 4.2(V) or less practically.
Since the backgate BG of the first transistor TN1, i.e., the potential of the P-well layer 2A, is connected to the ground line GND through the P.sup.+ type diffused layer 4C as shown in FIG. 40(b), the potential is at 0(V). This is equivalent to a negative bias voltage being applied when the backgate BG is seen from the source S (output terminal out) of the first transistor TN1, and the state that reverse bias is applied is presented more distinctly as the voltage level of the output terminal out is increased. With this, an apparent threshold voltage Vthb of the first transistor TN1 exceeds Vth=0.8(V), and a voltage equal to the ideal threshold voltage Vth=a voltage drop at one stage is not obtainable (FIG. 41(b)).
Besides, in FIG. 39(a) and FIG. 40(a), when an output level at potential 0(V) or less of the ground line GND is applied to the output terminal out, it flows out of the ground line GND to the output terminal out sometimes by means of the second parasitic diode D2 and the parasitic diode Dn, respectively. With this, the output level of the output circuit becomes unstable, and hence, the reliability of the semiconductor integrated circuit device is lowered sometimes.